Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
نویسندگان
چکیده
منابع مشابه
Process-Variation and Temperature Aware SoC Test Scheduling Technique
High temperature and process variation are undesirable phenomena affecting modern Systems-on-Chip (SoC). High temperature is a well-known issue, in particular during test, and should be taken care of in the test process. Modern SoCs are affected by large process variation and therefore experience large and time-variant temperature deviations. A traditional test schedule which ignores these devi...
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Reducing test cost by minimizing the overall test time is one of the main goals of System-on-Chip (SoC) test scheduling. Power-aware strategies optimize the overall test time of a test schedule for a global peak power budget. For powerconstrained test scheduling with multiple test clock frequencies, a fast heuristic method for sessionless test scheduling is proposed. Experiments on several ITC’...
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ژورنال
عنوان ژورنال: Journal of Electronic Testing
سال: 2008
ISSN: 0923-8174,1573-0727
DOI: 10.1007/s10836-007-5030-6